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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:03:51 09/27/2013 
-- Design Name: 
-- Module Name:    twos_complement_32 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity twos_complement_32 is
	port(	dataIn : in STD_LOGIC_VECTOR(31 downto 0);
			dataOut : out STD_LOGIC_VECTOR(31 downto 0));
	
end twos_complement_32;

architecture Behavioral of twos_complement_32 is
	component adder_32 
		 Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);
				  b : in  STD_LOGIC_VECTOR (31 downto 0);
				  carryIn : in  STD_LOGIC;
				  sum : out  STD_LOGIC_VECTOR (31 downto 0);
				  carryOut : out  STD_LOGIC);
	end component;
	signal a, b : STD_LOGIC_VECTOR(31 downto 0);
	signal carryIn, carryOut : STD_LOGIC;
begin
	adder : adder_32 port map(a, b, carryIn, dataOut, carryOut);
	a <= NOT(dataIn);
	b <= X"00000000";
	carryIn <= '1';
end Behavioral;

